Analog and RF Layout Engineer

This senior capacity at Capgemini in San Francisco oversees the physical layout of high‑speed analog and RF mixed‑signal blocks, guiding projects from concept through tape‑out and ensuring performance and manufacturability in 7nm and below FinFET technologies.

Location

San Francisco, CA, onsite

Compensation

USD 79,750 – 174,000 per year

Responsibilities

• Lead and contribute to the physical layout of complex, high‑speed analog and RF mixed‑signal blocks from concept to tape‑out
• Develop block‑level and chip‑level layouts in advanced CMOS FinFET technologies (7nm and below)
• Collaborate closely with analog, RF, and digital designers to ensure layout quality, performance, and manufacturability
• Own floor planning, block‑level routing, and top‑level chip assembly activities for advanced ICs
• Apply best‑in‑class layout techniques to address signal integrity, electromigration, thermal awareness, and high‑speed performance
• Lead layout reviews, layout verification, and design rule compliance using industry‑standard EDA tools
• Mentor junior engineers and promote engineering best practices and collaborative work

Requirements

• 6+ years of experience in analog and RF IC layout for high‑speed applications
• Hands‑on experience developing and leading layouts at both block and full‑chip levels in FinFET technologies (7nm and below)
• Strong expertise with industry‑standard EDA tools from Cadence, Mentor, and Synopsys
• Proven experience in layout of high‑performance analog mixed‑signal blocks, such as high‑speed transceivers
• Experience with CMOS drivers, high‑speed data converters, and PLLs
• Solid understanding of floorplanning, routing, layer generation, thermal‑aware layout practices, and electromigration considerations

Technologies

• Cadence
• Mentor Graphics
• Synopsys

Benefits

• Paid time off according to employee grade, including vacation, holidays, personal days, and sick leave
• Medical, dental, and vision coverage, with provincial coordination where applicable
• Retirement savings plans (such as 401(k) in the US or RRSP in Canada)
• Life and disability insurance
• Employee assistance programs
• Additional benefits as provided by local policy and eligibility

About the Job

As a Senior Analog / RF IC Layout Engineer, you will be pivotal in enabling cutting edge high‑speed mixed‑signal silicon for next generation technologies. You will work with top design, verification, and process teams to deliver robust, scalable layouts in advanced FinFET nodes, supporting high‑performance products across multiple industries.